1. Field of the Invention
The present invention relates to a memory interface and an operating method of the memory interface.
2. Description of Related Art
With advance of an information processing technique, a semiconductor memory device has spread which attains a high-speed operation and a low power consumption amount. In such a semiconductor memory device, a data strobe signal (DQS) is employed in order to achieve high-speed data communication. Examples of the semiconductor memory device using the data strobe signal (DQS) are such as DDR2 (Double Data Rate 2) SDRAM (Synchronous DRAM) and DDR3 SDRAM, which have a data transfer rate in a Gbps band.
Generally, a memory interface is provided between the semiconductor memory device and a CPU. The memory interface is mounted based on a result of board mounting simulation including an extended interconnection on a circuit board. In recent years, in the semiconductor memory device, even when the mounting according to the simulation result is achieved, variation in a delay time of an input/output buffer occurs depending on a relative accuracy of the mounting wiring and a temperature of the mounting board with a faster system clock signal and a lower power supply voltage due to an increase in a data rate. Thus, there is a demand for a memory interface circuit which can adjust the delay time depending on individual difference of an input/output buffer after completion of an LSI.
For example, to properly read/write data from/into a memory having a data transfer rate in a Gbps band, it is needed to properly design a circuit portion including internal flip-flops for capturing data read from the memory and a circuit portion for outputting the data from the flip-flops in synchronization with a system clock signal. To determine an effective period of the synchronized data, a technique is known of calculating Round-Trip-Delay in which a clock signal outputted from a memory controller returns to the memory controller as a data strobe signal DQS via a memory (SDRAM) (for example, Patent Literature 1).
FIG. 1 is a circuit diagram showing a configuration of a semiconductor device described in Patent Literature 1 (Japanese Patent Application Publication (JP-P2007-280289A)). In Patent Literature 1, arrival times of clock signal signals CK and CK# and a data strobe signal DQS which are transmitted to a double data rate memory are acquired by utilizing a reflected wave on a transmission path, and an effective period of data synchronized based on the arrival times of the clock signal signals and the data strobe signal is determined. Thus, the effective period of data synchronized with a system clock signal is determined according to an actual mounting state and connection environments.
Patent Literature 2 (Japanese Patent Application Publication (JP-P2007-12166A)) describes a technique relating on a semiconductor device which can adjust a difference between propagation characteristics due to individual difference or environmental difference. Patent Literature 3 (Japanese Patent Application Publication (JP-P2008-52335A)) describes a technique relating to an interface circuit for receiving a strobe signal outputted from a semiconductor device such as a memory and an LSI and a data signal synchronized with the strobe signal and adjusting a phase shift amount of the strobe signal for latching the data signal.
According to a conventional technique, a delay time is measured and the delay time is adjusted based on the measured result. However, according to the conventional technique, delays of a clock signal and a data strobe signal are measured by utilizing reflection on their transmission lines. For this reason, only the arrival times on the transmission lines and a delay of an input buffer on the side of an interface can be measured, and measurement cannot be performed in consideration of fixed delay amounts of the output buffers on a memory side and the interface side and jitter as a change amount at a normal read operation.
Since delay times of the output buffer and the memory cannot be measured, there is a case that synchronization with the internal system clock signal cannot be attained because of an unexpected large change of the delay times. Thus, an error in the system occurs. In this case, redesign of the transmission line and the I/O buffer is needed.
Moreover, a delay time of the clock signal and a delay time of the data strobe signal are separately measured. Thus, a measurement error of the delay time is sometimes regarded to be doubled.